Bài báo: “Enhance Security for the E-payment Application with Blockchain Technology”
Học viên thực hiện:
- Lê Huy Hùng - ATCL2021 - Tác giả chính
Giáo viên hướng dẫn:
- PGS.TS. Lê Trung Quân
- ThS. Nguyễn Khánh Thuật
Tóm tắt:
E-payment systems, despite their practicality, face challenges such as data manipulation, limited bandwidth, and potential denial-of-service attacks. These issues can impact businesses, financial institutions, and individual users conducting transactions, as they struggle to manage large amounts of traffic simultaneously. Addressing these issues is crucial for ensuring secure and efficient transactions. This research presents a system that integrates Hyperledger Fabric with software-defined networking to enhance system throughput without significantly altering the Blockchain’s functionality. It also uses Hyperledger Aries technology for improved client identity recognition efficiency. The proposed system aims to reduce deployment time, maintain secure data, and provide a non-stop payment platform for client identification within a decentralized framework. It supports multiple concurrent users or system attacks with minimal average delay, ensuring efficient communication among components. The system is being researched to find a feasible solution that balances security and performance in real time while minimizing internal platform modifications.
“Chúng em xin gửi lời cảm ơn đến Thầy Lê Trung Quân, Thầy Nguyễn Khánh Thuật đã tận tình hướng dẫn và chỉ ra những mặt thiếu sót, góp ý thêm để của chúng em hoàn thành được công trình nghiên cứu và công bố bài báo khoa học này".
Thông tin chung:
The International Conference on Integrated Circuits, Design, and Verification (ICDV) provides a forum for exchanging ideas, discussing research results, and presenting chips, circuit designs and applications in solid-state and semiconductor fields. Continuous scaling of the CMOS devices increases the number of transistors on a VLSI chip. It reaches the level of 100 giga transistors on a single chip, which is comparatively higher than the total neuron numbers in the human brain. This would certainly provide us a great opportunity for new applications and information processing. On the other hands, the small feature size causes new problems such as leakage current and process variation. To discuss utilizing the scaling advantages and coping with the new problems, we call for contributions about new proposal of application systems, VLSI architectures, and design methodologies as well as the technologies and applications in the integrated circuits and devices field. We expect to this conference explores and stimulates the contributed researches to those subjects. The papers are solicited from prospective authors interested in the related fields. The ICDV 2024 conference is organized by IEEE CAS Vietnam Chapter, co-hosted by VNU Information Technology Institute (VNU-ITI) and VNU International School (VNU-IS), technically supported by the IEEE SSCS Vietnam and the IEICE Vietnam Section. The ICDV 2024 will be held in Hanoi, Vietnam. Further information about the conference, paper submission guidelines and templates will be updated on the website.
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