Bài báo: “DDoS Attack Detection for Software-Defined Network Architecture Based on Artificial Intelligence”
Sinh viên thực hiện:
. Phạm Thái Bảo - ATCL2021 - Tác giả chính
. Nguyễn Lê Hạ My - MMTT2023.2 - Đồng tác giả
Người hướng dẫn:
. ThS. Văn Thiên Luân
. ThS. Nguyễn Khánh Thuật
. PGS.TS Lê Trung Quân
Tóm tắt:
The Software-Defined Networking (SDN) model provides significant advantages for network administrators by facilitating traffic initialization, control, and management. SDN optimizes bandwidth and resource utilization through efficient traffic routing and network management automation. Distributed Denial-of-Service (DDoS) attacks target websites and servers by disrupting network services and depleting application resources. In SDN, control functions are centralized in the control plane, while network devices handle packet forwarding. DDoS attacks in SDN impact all network layers, exploiting bandwidth and limiting infrastructure scalability. To mitigate DDoS attacks, Artificial Intelligence (AI)-based approaches, specifically Machine Learning (ML) and Deep Learning (DL), are integrated into Intrusion Detection and Prevention Systems for enhanced detection and response. Our proposed approach involves building an SDN network architecture, collecting traffic, and utilizing ML and DL models for DDoS detection. In ML models, feature extraction is performed before classification, while DL models preprocess network traffic by normalizing and converting it into images for classification. Among the evaluated models, Random Forest (RF) and DenseNet demonstrated the best performance, achieving a high accuracy of 99.87% and 99.4% while excelling in training time, inference speed, and model size.
"Chúng em xin trân trọng gửi lời cảm ơn đến thầy Nguyễn Khánh Thuật - Giảng viên tại Khoa Mạng máy tính và Truyền thông vì sự hướng dẫn tận tình cùng những định hướng rõ ràng ngay từ những bước đầu trong quá trình thực hiện nghiên cứu. Đồng thời, chúng em cũng xin bày tỏ lòng biết ơn sâu sắc đến các thầy, các anh đang giảng dạy tại Khoa đã luôn góp ý, chỉnh sửa những điểm còn hạn chế và tạo điều kiện thuận lợi để chúng em hoàn thành nghiên cứu và công bố bài báo khoa học này."
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The International Conference on Integrated Circuits, Design, and Verification (ICDV) provides a forum for exchanging ideas, discussing research results, and presenting chips, circuit designs and applications in solid-state and semiconductor fields. Continuous scaling of the CMOS devices increases the number of transistors on a VLSI chip. It reaches the level of 100 giga transistors on a single chip, which is comparatively higher than the total neuron numbers in the human brain. This would certainly provide a great opportunity for new applications and information processing. On the other hand, the small feature size causes new problems, such as leakage current and process variation. The ICDV 2025 conference is organized by IEEE CAS Vietnam Chapter, co-hosted by Vietnam National University Ho Chi Minh City – The University of Science (VNUHCM-US), technically supported by the IEEE SSCS Vietnam and the IEICE Vietnam Section. The ICDV 2025 will be held in Ho Chi Minh City, Vietnam. Further information about the conference, paper submission guidelines and templates will be updated on the website. Accepted and presented papers will be included in the conference proceedings with ISBN and will be submitted for inclusion in IEEE Xplore® (the copyright shall be assigned to the IEEE). The proceedings of ICDV series are regularly indexed by Scopus and listed in the conference proceeding citation index (CPCI) of Clarivate.
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